System-On-Chip, SOC, devices are semiconductor devices in which a single integrated circuit chip includes various different device types in the chip. The SOC device may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip, for example. In one particular example, a single chip may include a flash memory device portion, an SRAM device portion, a ROM device portion, digital logic circuitry, voltage pumps, voltage regulator devices, analog-to-digital converters, and so on. Each of the different device portions may be formed using different manufacturing operations and may require different operating characteristics.
One of the challenges in manufacturing various semiconductor devices and SOC devices in particular, is producing functionally different device portions such that their operational characteristics are compatible with one another. Low power SOC devices are devices that require low standby current. This condition must be met in all device portions. This operational characteristic would necessarily have to be compatible with each of the functional device portions of the SOC device since a high standby current in one of the device portions could adversely affect the operation of the entire SOC device.
Shallow Trench Isolation, STI, devices are used to electrically isolate active semiconductor structures from one another. This is true within and between the different device portions of an SOC device. For example, STI's may be used to isolate N-wells from P-wells. STI's may be used as such in any device portion, such as within an SRAM, Static Random Access Memory device. It has been found that STI edge junction leakage is one of the main sources of standby leakage. Low power SOC devices that require low standby current cannot operate with any significant level of standby leakage.
There is a tradeoff, however, between attempting to manufacture the various different device portions using common processing operations and minimizing the number of these processing operations, and delivering different operational characteristics to the different functional device portions as needed. For example, STI devices may be formed by forming trenches in a substrate and overfilling the trenches with an oxide or other dielectric material that is also formed over the surfaces of the substrate within which the trenches are formed. The oxide or other dielectric is then removed from over the substrate leaving the trenches filled with the dielectric. The STI structures may be formed to include a protrusion of the trench dielectric above the surrounding surfaces within which the trench is formed.
In SRAM devices, in particular in high density SRAM memory products, it is desirable to have STI structures that include such dielectric protrusions wherein the thickness of the dielectric protrusion is maximized in order to minimize standby current, thereby reducing standby current leakage and improving device performance. In flash memory devices, i.e. in the flash memory portion of an SOC device, in contrast, a split gate embedded flash process is commonly used and the split gate embedded flash process utilizes a double poly process, i.e. a process including multiple layers of polysilicon being deposited and patterned. The double poly process is inhibited, however, if the STI dielectric thickness is excessively thick, more particularly if the STI device includes a dielectric protrusion and the protrusion of the trench dielectric above the surrounding surface is great. A greater thickness of this dielectric protrusion creates greater steps that the polysilicon film traverses. This reduces the poly etch process window and may result in poly residue, such as polysilicon stringers formed along the edges of the STI structures where it is difficult to remove the polysilicon film using anisotropic polysilicon etching operations. The protrusion may even be tapered and include an overhang portion that may cover and obscure polysilicon material, making it more difficult to remove the polysilicon material in downwardly directed anisotropic etches. This poly residue often results in shorts or creates a leakage path between neighboring cells and induces flash cell failures.
Shallow Trench Isolation, STI, devices are conventionally formed by patterning and etching operations that create deep trenches etched into a semiconductor substrate, most typically a silicon substrate. The substrate upon which the SOC chips are being formed, is subjected to one sequence of patterning and etching operations commonly performed upon all areas of the substrate and all areas of the chip. The common sequence of patterning operations produces STI devices that are generally similar throughout the substrate and throughout the SOC device. The similar STI devices have similar dielectric thicknesses, i.e. if not completely coplanar with the substrate surface, the protrusions of the trench dielectric that extend above the surface generally have about the same height and same shape throughout an integrated circuit device, i.e. chip.
Regardless of the particular height or shape of any trench dielectric that may protrude above the surface, when all of the STI structures have about the same size and shape throughout the SOC device, any given height or shape will not be optimal in each of the different device portions. The STI may be the source of or contribute to problems in one or more of the different device portions since each device portion will have different optimum STI dielectric thicknesses and shapes.
The present invention addresses these concerns.